1. Field
Aspects in accordance with the present invention relate to a simulation apparatus, a simulation method, and a program.
2. Description of the Related Art
FIG. 2 illustrates a test bench for simulating a clock synchronization logic circuit that includes two flip-flops 103 and 104 and a combinational circuit 112 connected between the flip-flops. A test bench 101 is a system that includes a verification target circuit 102 and a test description.
A simple example of the verification target circuit 102 is described using the clock synchronization logic circuit including the two flip-flops 103 and 104 and the combinational circuit 112 connected between the flip-flops. Such a clock synchronization logic circuit is commonly used in semiconductor integrated circuits.
FIG. 3 is a timing chart illustrating an examplary operation of the verification target circuit 102. The number of cycles denotes the number of cycles of a clock signal CLK. In a cycle 1, the first flip-flop 103 holds data input into an input terminal DI in synchronization with a rise of the clock signal CLK, and outputs data FF1DO from an output terminal DO. The data FF1DO, in the cycle 1, reaches an input terminal DI of the second flip-flop 104 as data FF2DI via the combinational circuit 112. That is, in the one cycle, the output data FF1DO of the first flip-flop 103 reaches the input terminal DI of the second flip-flop 104 as the data FF2DI. Such a circuit is referred to as a single cycle path. In the single cycle path, data delay between the flip-flop 103 and the flip-flop 104 is within one cycle.
In a cycle 2, when a write-enable signal FF2WE is at a high level, the second flip-flop 104 holds the data FF2DI input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs data FF2DO from an output terminal DO. The second flip-flop 104, when the write-enable signal FF2WE is at a low level, holds the data without writing the data, and outputs the held data from the output terminal DO as the data FF2DO.
In the verification target circuit 102, if data delay is within N cycles at a maximum, any delay may be permitted. Such a state is referred to as a multi-cycle path. Here, N is a natural number more than one.
FIG. 4A is a timing chart for a situation where the verification target circuit 102 in FIG. 2 is a multi-cycle path of N cycles. Similarly to the above case, in the cycle 1, the first flip-flop 103 holds data input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs the data FF1DO from the output terminal DO. In response to the operation, since the input data FF2DI of the second flip-flop 104 is permitted to vary to a new value at a timing of any one of cycles 1 to 4, in the cycles 1 to 4, the value is an undefined value (undefined value of zero or one). The second flip-flop 104 is required to perform correct circuit operation even if the input data FF2DI varies during any one of the cycles 1 to 4.
When the write-enable signal FF2WE is at the high level, the second flip-flop 104 holds the data FF2DI input into the input terminal DI in synchronization with a rise of the clock signal CLK, and outputs the data FF2DO from the output terminal DO. Accordingly, the output data FF2DO has an undefined value during cycles 2 to 4.
In the circuit, the output data FF1DO of the first flip-flop 103 in the cycle 1 reaches the input terminal DI of the second flip-flop 104 as the data FF2DI in any one of the cycles 1, 2, 3, to N. In order to use the circuit as a multi-cycle path, it is necessary to design the circuit such that even if the input data FF2DI of the second flip-flop 104 varies in any one of the cycles 1, 2, 3, to N, the circuit correctly operates.
Generally, the multi-cycle path is intentionally designed by a circuit designer. In the description below, it is assumed that paths of the multi-cycle path are described in timing constraint information (Design Constraints) or the like that is used as standard input information in circuit specifications, logic synthesis, layout, wiring, and static timing analysis that are development flows after logic verification.
In the description, the development of the semiconductor integrated circuit is implemented in accordance with steps of, as a first step, implementing design of a logic circuit at a register transfer level (hereinafter, referred to as RTL) (logic design), as a second step, verifying validity of the logic circuit (logic verification), as a third step, synthesizing the verified logic circuit to a gate level (logic synthesis), as a fourth step, laying out and wiring the synthesized circuit (layout and wiring), and as a fifth step, implementing timing verification (static timing analysis (STA)). Further, in the specification, gate level simulation that includes delay is described. It is assumed that the gate level simulation is implemented as a sixth step after the static timing analysis is completed.
Now, problems where the multi-cycle path is verified at RTL are described. When the circuit designer verifies operation of the multi-cycle path as a logic circuit, with respect to a signal defined as a multi-cycle path, and additionally verifies whether the signal can actually be used as the multi-cycle path it is necessary to verify the logic circuit operation in consideration of delay.
This is because, in the multi-cycle path, it is necessary to check whether the operation of the multi-cycle path is normal even if data delay in a period, when the output data FF1DO of the first flip-flop 103 reaches the input terminal DI of the second flip-flop 104 as the data FF2DI, is in any one of the cycles 1, 2, 3, to N.
Normally, the operation verification in the logical verification is implemented at RTL without delay. If the delay is not included, it is difficult to verify whether the multi-cycle path of N cycles operates normally even when the data delay is at any one of the cycles 1, 2, 3, to N. Hereinafter, the reason is described.
FIG. 4B is a timing chart where logical verification of a multi-cycle path is implemented at RTL. At RTL, gate delay and wiring delay between the flip-flop 103 and the flip-flop 104 is not considered. Accordingly, if the output data FF1DO of the first flip-flop 103 varies in the cycle 1, the input data FF2DI of the second flip-flop 104 also varies in the same cycle 1. In the next cycle 2, the output data FF2DO of the second flip-flop 104 is fixed to a new value.
If the timing chart in FIG. 4B is compared to the timing chart of the single cycle path in FIG. 3, it is understood that, in both cases, the operation of the second flip-flop 104 at the rise timing of the clock signal CLK is the same. This means that, in both cases, the operation is the same as verification of the single cycle path. Further, if the timing chart in FIG. 4B is compared to the operational view of the multi-cycle path of N cycles in FIG. 4A, it is understood that, in the operation of the second flip-flop 104, at the rise timing of the clock signal CLK, the values are different from values originally expected in the multi-cycle path in cycles 2 to 4. Accordingly, it is understood that it is not possible to correctly verify the multi-cycle path in the logical simulation at RTL.
As the method to perform verification of operation of a logic circuit in consideration of delay, two methods described below have been known.
In the first method, the verification is performed by gate level simulation that is performed after the circuit is laid out and wired. In the gate level simulation to be performed after the circuit is laid out and wired actual gate delay and wiring delay is contained. Accordingly, it is possible to consider data delay in the multi-cycle path.
The first method is excellent in verifying that the specific semiconductor integrated circuit correctly operates. However, the verification is performed in the state that the gate delay and the wiring delay have values unique to the semiconductor integrated circuit. Accordingly, in the verification, the operation (FIG. 4A) of the multi-cycle path of N cycles, where the data variation is in any one of the cycles 1, 2, 3, to N, the correct operation of the multi-cycle path is not verified.
Further, to perform the logical simulation with the gate delay and the wiring delay, it is necessary to perform the simulation after the logic synthesis, the layout, the wiring, the static timing analysis (STA), and the like. These are the development flows performed after the logic verification is performed. Accordingly, a large amount of additional man-hours are required for returning to the job when a malfunction is found in specifying the multi-cycle path. Especially, in the development of current semiconductor integrated circuits that are growing in scale, a loss of efficiency during the development period is very serious.
As the second method, in Japanese Patent Application Laid-Open Publication No. 2006-318121, a method to intentionally apply delay to a target part in RTL verification is described. In the RTL description, it is possible to add a delay value to a specific signal. The function can be used in many simulation apparatuses. Accordingly, it is possible to reproduce pseudo logical verification with consideration of delay.
However, in the second method, the delay value that can be applied in one logical simulation is a constant value. Accordingly, similar to the first method, in the second method, in order to verify that the multi-cycle path of N cycles operates correctly (FIG. 4A) when the data variation is at any one of the cycles 1, 2, 3, to N, it is necessary to perform logical simulation at least N times with respect to one multi-cycle path, and it is not efficient.
For example, in a case where a plurality of multi-cycle paths of N cycles exist in a circuit, and the paths are operationally associated with each other, it may be necessary to consider combinations of delay values to be applied to the individual multi-cycle paths. As a result, the number of combinations necessary for the verification becomes enormous.
Further, as a third method, in Japanese Patent Application Laid-Open Publication No. 2001-273351, a technique to analyze a circuit configuration at RTL or a gate level and provide a part that can be defined as a multi-cycle path has been described. The method is effective to exhaustively search for multi-cycle paths including a multi-cycle path unintentionally made by the circuit designer.
However, in the multi-cycle paths in the circuit, in addition to a multi-cycle path defined by the circuit configuration, many parts that can be defined as multi-cycle paths by reasons depending on the specification, or the other logical circuits exist. Accordingly, it is difficult to determine whether multi-cycle part information described in the circuit specification or the like is really correct using only this technique.